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The OrCAD® and Allegro® 22.1 release is now available at Cadence Downloads. This blog post contains important links for accessing this release and introduces some of the main changes made and the new features that you can look forward to.
OrCAD/Allegro 22.1 (SPB221)
Here is a representative list of the changes and enhancements across products with brief overviews.
Allegro PCB Editor and Allegro Package Designer Plus
- Many performance enhancements have been made in this release, such as faster Update to Smooth, better move performance, faster DRC checking for designs with negative layers, and so on. Also included are display-related enhancements, namely expanded GPU support and normalized forms for high resolution displays.
- A new 3DX engine is integrated with the Allegro board design database to address scale and complexity issues for large designs.
- High-speed structures get created faster maintaining the current routing and delayed matching without pad entry or exit traces. Several utilities are introduced to convert, create, or replace objects with padstacks directly on the canvas. This comes handy when converting the GERBER or DFX files into intelligent designs. You no longer need to convert these files to a different design object to establish connectivity. Even generating custom shapes based on clines, lines, pins, or via pads is possible instead of tracing objects manually.
- You can now change a dimension without deleting or regenerating it by first separating the dimension symbol into individual objects and then changing the objects.
- Using Power Delivery Generator, you can build plane areas based on the location of the pins in the layout instead of defining plane areas by highlighting power nets and then looking for clusters.
Sigrity Aurora
- A non-analysis version of Topology Workbench for capturing constraints is now included with Allegro PCB Editor and Allegro Package Designer Plus.
- The latest Analysis Model Manager module is integrated with Sigrity Aurora similar to the other Sigrity applications and workflows.
- In the Interconnect Model Extraction Workflow, you can now define manufacturing tolerances around a layout database. This automates the extraction of high and low impedance scenarios along with the as-designed cases.
- In the Design Setup Workflow, the Set up Padstack Plating Parameters option is added to globally define the via plating thickness.
Allegro Pulse
When publishing derived data from boards to a PLM system, the source of the board files is also defined in the Publish for Manufacturing (PFM) application. Until now, the source of the board files could be a local directory or a shared folder. From this release, you can also specify Pulse as the source of the board files. This ensures that the boards are always in sync with the front-end designs.
Allegro System Capture
- Performance and response time improvements are made which you can notice when working on schematics, such as when opening and saving designs, a new real-time algorithm for junction calculation and improved data caching has made wiring performance better, and canvas selection is also improved by 3x to 5x for large schematic selections.
- Many visual cues have been added that make tracking nets easier than before. You can also flag base or winning nets and include the block prefix and suffix text in physical net names.
- Designs can be opened as read-only to avoid any accidental overwriting or unnecessary locking of designs.
- You can now configure the default naming of nets when connected to a power source or while copying the circuitry. New preferences are available to add or display the signal name on wires when connected to a power source, and to control the transfer of the hidden power signal name—if the hidden named and ‘unnamed_*’ signal names should be transferred when pasting a selection.
- Until now, the Reference Designator (Ref Des) for multi-section instances or split instances would change when parts were processed sequentially. Now, all sections are processed as a single transaction and this enables Ref Des preservation after Part Manager updates.
- Deleted bus bits are automatically purged and the explicit user action for this is no longer needed.
- You can now replace components in variants with placeholders. Preferred parts are no longer restricted to parts available in the project libraries. In addition, you can mark components on the base design also as Do Not Install (DNI).
- When working with system-level designs, you can quickly identify the nets that are perfect or partial matches when assigning ports and pins using color coding. Printing system-level designs to all print formats, such as print, PDF, or Smart PDF is also supported similar to printing schematic designs.
- From this release, in addition to the .brd files from PCB Editor, you can now also link the .MCM files from APD Plus with Allegro System Capture schematics.
- On the library management side, you can now create DE-HDL libraries and even edit parts within System Capture when working in a DE-HDL libraries project. Additionally, you can create a new or edit an existing OLB schematic model .
Topology Workbench
- The Topology Workbench executable file is renamed to TopWb.exe from TopXp.exe.
- The SystemSI workflow now complies with the IBIS 7.1 specifications and enables modeling of complex packages. The Trace Editor interface is enhanced.
- Cable Modeler is enhanced to support coaxial cables. In the T-Line Type list, you can also choose Coaxial Cable and set the parameters.
- Topology Workbench supports PCI Express Gen 6 Compliance kit, which enables you to simulate PAM4 signaling.
- In the SystemPI workflow, the modified Voltus files are now saved in the asi_models directory, which enables the editing of Voltus Model PWLs. You can now specify the start and stop time for a waveform, and even repeat the waveform for the required number of times.
PSpice A/D
- This release provides a convenient way to implement an impedance that varies with frequency, using frequency tables in the CSV format.
- The support for expressions in PSpice Modeling Application has now been extended to digital clock source, DigClock.
- Noise Analysis is enhanced to list top noise contributors in the Noise Analysis tabular report. This enables you to identifythe primary noise contributors quickly without going through any manualcalculations.
- Circuits can now be simulated with zero value resistors. All the zero values are replaced by GMIN, which is set to 1.0E-12 by default.
- Monte Carlo analysis is enhanced to calculate and report 3-Sigma and 6-Sigma values. The sigma values are shown as columns in the Monte Carlo statistical results grid.
- With Smoke analysis, you can enable automatic deration of power. If custom deration is defined for a resistor, its power dissipation is derated with temperature. The calculated derating value is displayed in the Smoke results
- Using Smoke Analysis, hierarchical components can now be filtered by using an asterisk to match any pattern following or preceding a string. You can use the Component Filter command to search for the components.
These were some of the top changes that are available in Cadence OrCAD and Allegro Release 22.1 release. For more information on the new features and enhancements made across products, see What’s New in Release 22.1on the Cadence Support portal.
We’ll soon be back with more in-depth blog posts on the new features and enhancements made across products, so watch this space.
In case you have questions or feedback, send them topcbbloggers@cadence.com.
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Allegro Release Team
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